MyHDL Project #2: Flexible Multiplexer Demultiplexer

https://github.com/fwswdev/MyHDLCollection/blob/master/02_FlexibleMuxDemux.py

This is a MyHDL program that contains multiplexer and demultiplexer. They both share a group of select pins. Users can change the number of mux and demux by just simply changing the BIT_WIDTH constant.

Few years back, I designed a UART Multiplexer/Demultiplexer using lots of 74HC4051. If I only knew MyHDL and XC2C128 by that time, my design could have been more compact. :)

MyHDL Project #1: Two Counters with 2 to 1 Multiplexer

Recently, I had been studying MyHDL with Xilinx CoolRunner XC2C128 CPLD. MyHDL is a very good software. I can simply reuse my existing Python skills and get started quickly with HDL designs.

https://github.com/fwswdev/MyHDLCollection/blob/master/01_TwoBlinkingLightsWith2to1Mux.py

This is a MyHDL program that has two counter (fast and slow) that outputs square waves. The counters are being controlled by a rising edge clock signal coming from a square wave signal generator (on my experiment, I used a 555 timer on astable mode). It is then fed into a 2 to 1 mux. This is tested working with XC2C128, Xilinx ISE 14.7, and Bus Pirate as the programmer.


This is the resulting test bench waveforms (I modified the internal counters to 5 and 10)

Special Thanks to this Online Wave Viewer  http://www.edaplayground.com/w/home