I am currently reverse-engineering an audio analysis algorithm which computes for the statistical variance. I needed to get around 100,000 A/D data points from the MSP430's FRAM microcontroller so that I can inject it to my unit test. With that, IAR gives me a TI-TXT format.
example:
@10000
30 20 40 50
60 70 80 90
I needed to convert this to a C array so that I can place this inside my C++ code. Here are the steps I did:
1. I extracted all the data and placed them inside a list which is very easy to do using split, appending "0x" and using join. The output will be like this:
"0x30, 0x20, 0x60" so on so forth
2. My problem with the above string is that it will take only one line of my C++ code which I feel won't look nice as I don't want to be scrolling horizontally as much as possible. I thought of creating a python algorithm to put newlines nicely without cutting a whole string like:
0x30, 0x20 ,0x
60, 0x70, 0x8
0, 0x20
Then I discovered python already covers it for me via textwrap module which I think is a smart algorithm. So now, I won't have any broken string and it will be printed nicely:
0x30, 0x20 ,0x60,
0x70, 0x80, 0x20
More information on how to use it here: https://pymotw.com/2/textwrap/
Showing posts with label python. Show all posts
Showing posts with label python. Show all posts
Friday, 9 February 2018
Thursday, 11 February 2016
MyHDL Project #2: Flexible Multiplexer Demultiplexer
https://github.com/fwswdev/MyHDLCollection/blob/master/02_FlexibleMuxDemux.py
This is a MyHDL program that contains multiplexer and demultiplexer. They both share a group of select pins. Users can change the number of mux and demux by just simply changing the BIT_WIDTH constant.
Few years back, I designed a UART Multiplexer/Demultiplexer using lots of 74HC4051. If I only knew MyHDL and XC2C128 by that time, my design could have been more compact. :)
This is a MyHDL program that contains multiplexer and demultiplexer. They both share a group of select pins. Users can change the number of mux and demux by just simply changing the BIT_WIDTH constant.
Few years back, I designed a UART Multiplexer/Demultiplexer using lots of 74HC4051. If I only knew MyHDL and XC2C128 by that time, my design could have been more compact. :)
MyHDL Project #1: Two Counters with 2 to 1 Multiplexer
Recently, I had been studying MyHDL with Xilinx CoolRunner XC2C128 CPLD. MyHDL is a very good software. I can simply reuse my existing Python skills and get started quickly with HDL designs.
https://github.com/fwswdev/MyHDLCollection/blob/master/01_TwoBlinkingLightsWith2to1Mux.py
This is a MyHDL program that has two counter (fast and slow) that outputs square waves. The counters are being controlled by a rising edge clock signal coming from a square wave signal generator (on my experiment, I used a 555 timer on astable mode). It is then fed into a 2 to 1 mux. This is tested working with XC2C128, Xilinx ISE 14.7, and Bus Pirate as the programmer.
This is the resulting test bench waveforms (I modified the internal counters to 5 and 10)
Special Thanks to this Online Wave Viewer http://www.edaplayground.com/w/home
https://github.com/fwswdev/MyHDLCollection/blob/master/01_TwoBlinkingLightsWith2to1Mux.py
This is a MyHDL program that has two counter (fast and slow) that outputs square waves. The counters are being controlled by a rising edge clock signal coming from a square wave signal generator (on my experiment, I used a 555 timer on astable mode). It is then fed into a 2 to 1 mux. This is tested working with XC2C128, Xilinx ISE 14.7, and Bus Pirate as the programmer.
This is the resulting test bench waveforms (I modified the internal counters to 5 and 10)
Special Thanks to this Online Wave Viewer http://www.edaplayground.com/w/home
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